The present invention provides a method and apparatus for generating delays to shift edges of an EFM data stream from an EFM modulator for a CD-R (Compact Disc Recordable) and CD-RW (Compact Disc, Re-Writable) write encoder.
In reading data from or writing data to a compact disc (CD), a number or series of pulses may be required in order to accurately read data from the disc or write data to the disc. Accuracy in generating these pulses is essential if data is to be properly read or written.
Prior art CD controlling circuits are known in the art, in which information is recorded in a PCM (pulse code modulation) format. Such devices are disclosed, for example, in U.S. Pat. No. 5,923,628, issued Jul. 13, 1999, U.S. Pat. No. 5,189,657, issued Feb. 23, 1993, or U.S. Pat. No. 4,532,561, issued Jul. 30, 1985, all of which are incorporated herein by reference.
Prior art CD systems may utilize a CD in which digital information is recorded in an EFM (eight-to-fourteen Modulation) format. In order to increase recording density, a CD may utilize CLV (Constant Linear Velocity) type encoding in which linear velocity of the disc is maintained at a constant speed regardless of where on the disc, from the inner periphery to the outer periphery, the signal is recorded. Therefore, rotational velocity of disc must be changed in accordance with the reading position in a radial direction of the disc. For this purpose, a control is carried out to calculate the present linear velocity from a synchronous signal pulse included in a signal read out from the disc, and to maintain linear velocity at a predetermined constant velocity.
In a CD modulation system, the frequency of a clock for providing reference signal CLK may be 4.3218 MHz, or a clock period of T=1/4.3218 MHz. Information may be recorded by patterns having the width (or duration) of three to eleven times of the clock period T (namely, 3T to 11T). This information recording is performed in units of one frame which is composed of 588 bits, namely, 588T, and an information recording region or section is so configured such that two or more maximum pattern widths of 11T are never contiguous.
One Prior Art rewritable compact disc drive system is shown in a block diagram of FIG. 1. During a write sequence, digital data from a host processor (not shown) is transferred to CD-ROM encoder 61 via host interface 76. The digital data may be made into an 8-bit signal with an error correction bit in an error correction circuit 62, which is applied to an eight-to-fourteen modulation (hereinafter referred to as EFM) circuit 63. Then, the 14-bit EFM signal may be applied to a write pulse generator 64 from which output is sequentially written on the optical disc 68 through a laser power controller 65 and pickup 66.
In the read sequence, the pickup reads out the written signal from the disc to convert the signal into an electrical signal and then deliver the signal into a pre-amplifier 69 for amplifying to an adequate level. The amplified analog signal is then applied into a slicing and reshaping circuit 72, a tracking circuit 70 and a focusing circuit 71. The analog signal of the pre-amplifier is digitized in the slicing and reshaping circuit and is then applied to an EFM demodulation circuit 73 to obtain a demodulated EFM signal, which is input to a CD-ROM decoder 75 through an error correction circuit 74. CD-ROM decoder 75 may interface with a host processor (not shown) though host interface 76.
In this optical reproducing system however, a number of write pulses must be changed depending upon a duty period of logic high level of the EFM signal to be written onto the disc during the write operation. Moreover, the timing of such write pulses needs to be accurately controlled such that the pulses produce accurate patterns on the CD.
In the Prior Art, timing of such pulses was largely controlled through the use of fixed delay elements. Such fixed delay elements could be provided to delay writing pulses by predetermined amounts in order to synchronize such write pulses with the operation of the disc.
Variations in temperature, voltage, and process (e.g., the manufacturing process for the controller chip or chips) can produce variations in timing parameters in such prior art devices. Thus, a requirement remains in the art to provide a CD read/write controller which can accurately and consistently produce delays for read and write signals.
These variations were not as critical in early CD-R and CD-RW models running at 1xc3x97, 2xc3x97, and 4xc3x97 speeds. However, as the speed of CD-R and CD-RW devices has increased to 8xc3x97 and beyond, the timing of write pulses becomes more critical. Prior art delay generation techniques using fixed delays may not accurately generate delays in write pulses at such speeds, particularly with the variations due to temperature, voltage and process.
The present invention provides a method and apparatus for generating delays to shift edges of an EFM data stream from an EFM modulator for a CD-R and CD-RW write encoder. The EFM data pulse edges (CD-R is a single pulse modulation, CD-RW is a multiple pulse modulation) can be delayed in increments of about {fraction (1/32)} Tefm where Tefm is the code rate clock of an EFM data stream output.
The method and apparatus of the present invention provides for generating robust and stable delays which are independent of temperature, voltage, and process variations. The delays are generated by a synthesizer running at four times the EFM code rate. The synthesizer may be built using a four-stage ring oscillator. Delays are selectable based upon the write strategy matrix in coarse increments of xc2xc T and fine increments of {fraction (1/32)} T.
For the coarse delay; the EFM data may be passed through a four stage shift register running at Fsynth, where Tefm=4xc3x97Fsynth, allowing for a coarse delay selection of xc2xd Tefm. The four stages of the ring oscillator provides eight phases of the synthesizer, each phase shifted by xe2x85x9 Tsynth thereby providing a delay selection of xe2x85x9 within each Tsynth period, translating into {fraction (1/32)} Tefm resolution. The advantage of this method is that delays may always be fixed with respect to the EFM code rate in {fraction (1/32)} Tefm increments and are independent of variations in temperature, voltage, or process variations.
The method and apparatus of the present invention may be extended to even finer delays by increasing the number of stages in the ring oscillator. Resulting delay increments would be Tefm/(2*N*M) wherein N is defined as the number of ring oscillator stages and M is the coarse delay.